1. Field of the Invention
The present invention relates to an active matrix type display device and a method for driving the same. In particular, a duty ratio of a pulse for driving signal lines of the active matrix type display device is controlled based on an analog video signal according to the present invention.
2. Description of the Related Art
In recent years, high-resolution display devices which are suitable for high-vision television, personal computers, or work stations have been developed. Among these kinds of display devices, active matrix type liquid crystal display devices have such a structure that signal lines and scanning lines are formed within a liquid crystal panel in a matrix shape, with switching elements (such as thin film transistors) being provided at intersections thereof. In such a liquid crystal display device, the respective horizontal lines of switching elements are driven so as to be on and off in a sequential manner. As a result, a signal voltage is selectively provided for pixel electrodes, thereby exciting liquid crystal interposed between pixel electrodes and a counter electrode. By modulating light transmitted through the liquid crystal layer with the signal voltage, gray-scale display or full-color display can be attained.
The signal voltage is supplied by a signal line driving circuit connected to the signal lines within the display panel. The signal line driving circuit is generally classified into analog driver (hereinafter referred to as "AD") type signal line driving circuits and digital driver (hereinafter referred to as "DD") type signal line driving circuits. An AD signal line driving circuit receives analog video signals as input signals. A DD signal line driving circuit receives digital video signals as input signals.
In the present specification, a driving element including signal line driving circuits corresponding to individual signal lines may collectively be referred to as a "signal line driver" for conciseness.
FIGS. 15 and 16 are diagrams for describing conventional AD signal line driving circuits. FIG. 16 shows all the signal line driving circuits corresponding to a number N of signal lines. FIG. 15 shows a signal line driving circuit corresponding to an i.sup.th signal line (where i represents an integer). As shown in FIG. 15, the AD signal line driving circuit is controlled by a sampling capacitor Csmp, a hold capacitor CH, an analog signal SW1 which is controlled by a sampling pulse Tsmp(i), an analog signal SW2 which is controlled by an output pulse OE, and an output stage analog buffer 230. The sampling capacitor Csmp is designed so as to have a sufficiently large capacitance as compared with that of the hold capacitor CH.
The operation of the AD signal line driving circuit is described using a signal timing diagram shown in FIG. 17. An analog video signal Va input to the analog switch SW1 is sequentially sampled with sampling pulses Tsmp(1) to Tsmp(N), which correspond to the respective N pixels on one scanning line that is selected for every pulse of a horizontal synchronization signal Hsync. As a result of the sampling, momentary voltages Vsmp(1) to Vsmp(N) of the analog video signal Va which are taken at respective points of time, are applied to the respective sampling capacitors Csmp.
An i.sup.th sampling capacitor Csmp is charged by a voltage value Vsmp(i) of the analog video signal Va that corresponds to the i.sup.th pixel, and retains that value. The signal voltages Vsmp(1) to Vsmp(N), which have been sequentially sampled and thus retained, are transferred from the respective sampling capacitors Csmp to the corresponding hold capacitor CH in accordance with an output pulse OE, which is simultaneously supplied to all the analog switches SW2. Thus, the signal voltages Vsmp(1) to Vsmp(N) are output to the signal lines S(1) to S(N) connected to the respective pixels via the output stage analog buffers 230.
In the case of a liquid crystal display device employing the AD method, the light transmittance characteristics of the liquid crystal, i.e., the relationship between the voltage applied to the liquid crystal and the display luminance by the liquid crystal are not linear, as shown in FIG. 23. As a result, a luminance offset emerges when an analog video signal itself is input to the analog driver. Therefore, it is necessary to process the input analog video signal in such a manner as to correspond to the transmittance characteristics of the liquid crystal.
Moreover, in the case of a liquid crystal display device, liquid crystal material may deteriorate if a d.c. voltage is applied thereto, so that a signal processing circuit for achieving a.c. driving is required. FIG. 29 shows an exemplary circuit thereof. FIG. 30 shows a timing diagram for describing an exemplary operation of the circuit of FIG. 29. In FIG. 29, reference numerals OP10 and OP20 denote analog operation amplifiers; reference numerals SW10 and SW20 denote analog switches; INV10 denotes a logic inversion circuit (inverter). The analog video signal Va is coupled to a plus terminal of the operation amplifier OP10 and a minus terminal of the operation amplifier OP20. A variable d.c. voltage Vset for offset adjustment is coupled to a minus terminal of the operation amplifier OP10 and a plus terminal of the operation amplifier OP20. The outputs of the operation amplifier OP10 and OP20 are coupled to one terminal of the analog switch SW10 and SW20, respectively, whereas the other terminals of the analog switches SW10 and SW20 are connected to each other. Thus, the analog video signal Va is output as an a.c. analog video signal Va'. A polarity inversion signal POL controls the analog switch SW10 directly and controls the analog switch SW20 indirectly via the inverter INV10. As shown in FIG. 30, the analog video signal Va is a video signal commonly used for display by cathode ray tubes or the like. The polarity inversion signal POL is a signal which varies in synchronization with the horizontal synchronization signal Hsync. Accordingly, when the polarity inversion signal POL is at a high level, the analog switch SW10 is turned on so that the output of the operation amplifier OP10 is output, as shown in FIG. 30. When the polarity inversion signal POL is at a low level, the analog switch SW20 is turned on so that the output of the operation amplifier OP20 is output, as shown in FIG. 30. Thus, the a.c. analog video signal Va' is obtained. The a.c. analog video signal Va' is a signal whose polarity is inverted as shown in FIG. 30. By applying the a.c. analog video signal Va' to the conventional analog driver shown in FIGS. 15 and 16, a.c. driving is realized. In the present specification, the term "analog video signal" is defined to include both general analog video signals employed for display using CRTs (cathode ray tubes) and analog video signals which have been converted into a.c. signals.
FIGS. 18 and 19 are diagrams for describing conventional DD signal line driving circuits. FIG. 19 shows all the signal line driving circuits corresponding to a number N of signal lines (this corresponds to the AD signal line driving circuits shown in FIG. 16). FIG. 18 shows a signal line driving circuit corresponding to an i.sup.th signal line (where i represents an integer; this corresponds to the AD signal line driving circuit shown in FIG. 15). For conciseness, it is assumed that the input digital video signals are composed of 2 bits, namely, D0 and D1. That is, video data has four values of 0, 1, 2, and 3. The gray-scale voltage to be provided for each pixel is one of the four levels V0, V1, V2, and V3.
The signal line driving circuit shown in FIG. 18 includes the first D flip-flop (sampling flip-flop) Msmp, the second D flip-flop (hold flip-flop) MH, a decoder DEC, and analog switches ASW0 to ASW3 provided between the respective external gray-scale voltages V0 to V3 and the signal line S(i).
The operation of this signal line driving circuit is as follows. Video signal data D0 and D1 are taken into and retained in the sampling flip-flop Msmp, responsive to the rise of the sampling pulse Tsmp(i) corresponding to the i.sup.th pixel. An output pulse OE is supplied to the hold flip-flop MH when the sampling for one horizontal scanning period has finished, so that the video signal data D0 and D1 retained in the sampling flip-flop Msmp are taken into the hold flip-flop MH and output to the decoder DEC. The decoder DEC decodes the 2-bit video signal data D0 and D1, and places one of the analog switches ASW0 to ASW3 in a conductive state, so as to output the corresponding one of the external gray-scale voltages V0 to V3 to the signal line S(i).
Apart from the conventional DD method, a binary multiple gray-scale signal line driving circuit which realizes multiple gray-scale display by only inputting two voltage levels of high and low and a plurality of digital gray-scale oscillation signal, without requiring any external gray-scale voltages or internal analog switches is disclosed in Japanese Laid-Open Patent Publication No. 6-27900.
Prior to describing the operation principles of this binary multiple gray-scale signal line driving circuit, an active matrix type liquid crystal panel display device will be described.
FIG. 12 shows one display device of an active matrix type liquid crystal panel. FIG. 13 shows a schematic equivalent circuit thereof. In FIG. 13, the resistance component of a signal line is denoted as Rsource; the capacitance component thereof is denoted as Csource; the ON resistance of a switch element T (i,j) is denoted as RON; and the capacitance of the display device P(i,j) is denoted as CLC. In the case where a storage capacitance is provided in order to increase the voltage retention ratio of the pixel, the pixel capacitance CLC is a sum of the liquid crystal capacitance (liquid crystal cell) constituted by a liquid crystal layer interposed between a pixel electrode and a counter electrode plus the storage capacitance provided in parallel to the liquid crystal capacitance.
In general, RON is sufficiently larger than Rsource; Csource is sufficiently larger than CLC; and the time constant (RON.times.CLC) of the display device is sufficiently larger than the time constant (Rsource.times.Csource) of the signal line. In other words, the path from the output of a signal line driving circuit to a liquid crystal cell of an active matrix type liquid crystal display device has the characteristics of a low-pass filter. The characteristics are substantially determined by the time constant (RON.times.CLC) of the individual display device, rather than the time constant (Rsource.times.Csource) of the signal line itself.
The binary multiple gray-scale signal line driving circuit disclosed in Japanese Laid-Open Patent Publication No. 6-27900, supra, utilizes the above-described low-pass filter characteristics of each display device as a fundamental principal, so that the output of the signal line driving circuit has only two levels of high and low, namely, VSH and VSL. In other words, as shown in FIG. 14, the signal line driving circuit outputs a signal having a period of T, an amplitude of (VSH-VSL), and a duty ratio (i.e., VSH output time: VSL output time) of m:n. By setting the period T of the output of the signal line driving circuit at such a value that the output is sufficiently averaged by the above-mentioned low-pass filter, an average voltage of (m'VSH+n'VSL)/(m+n) is charged in the pixel. Accordingly, it is possible to charge the pixel with a desired voltage by adjusting the output duty ratio m:n of the signal line driving circuit.
FIG. 20 is a diagram for describing the constitution of the binary multiple gray-scale signal line driving circuit described in Japanese Laid-Open Patent Publication No. 6-27900. FIG. 20 shows a signal line driving circuit for providing four levels of voltage corresponding to two-bit data, the signal line driving circuit corresponding to the i.sup.th signal line (this corresponds to the conventional digital driver shown in FIG. 18). In FIG. 20, the operation based on a sampling flip-flop Msmp, a hold flip-flop MH, a sampling pulse Tsmp(i), and an output pulse OE, and the outputs Y0 to Y3 of a decoder DEC are the same as those of the circuit shown in FIG. 18. AND circuits 802 and 803, and a three-input OR circuit 804 are provided on the output side of the decoder DEC. Signals TM1 and TM2 (described later) are supplied to the other input of the AND circuits 802 and 803, respectively.
FIG. 21 shows the waveforms of the signal, TM1 and TM2. The duty ratio of the signal TM1 (i.e., the ratio between periods [m] in which the pulse is at "1" and periods [n] in which the pulse is at "0") is such the m:n=1:2. The duty ratio of the signal TM2 is such that m:n=2:1.
When video data (D0, D1)=(0, 0) is input to this binary multiple gray-scale signal line driving circuit, the output Y0 of the decoder DEC shifts to "1", and the other outputs Y1 to Y3 shift to "0". Since the inputs of the OR circuit 804 are all "0", the output of the OR circuit 804 is at VSL, as shown in FIG. 22A.
When video data (D0, D1)=(0, 1) is input, the output Y1 of the decoder DEC shafts to "1", and the other outputs Y0, Y2, and Y3 shift to "0". Accordingly, the output of the OR circuit 804 has a pulse waveform oscillating between VSH and VSL at the same duty ratio of m:n=1:2 of the signal TM1, as shown in FIG. 22B.
When video data (D0, D1)=(1, 0) is input, the output Y2 of the decoder DEC shafts to "1", and the other outputs Y0, Y1, and Y3 shift to "0". Accordingly, the output of the OR circuit 804 has a pulse waveform oscillating between VSH and VSL at the same duty ratio of m:n=2:1 of the signal TM2, as shown in FIG. 22C.
When video data (D0, D1)=(1, 1) is input to this binary multiple gray-scale signal line driving circuit, the output Y3 of the decoder DEC shifts to "1", and the other outputs Y0, Y1, and Y2 shift to "0". As a result, the output of the OR circuit 804 is at VSH, as shown in FIG. 22D.
Thus, when video data (D0, D1)=(0, 0) is input, the output voltage VSL of the signal line driving circuit itself is applied to the pixel. When video data (D0, D1)=(1, 1) is input, the output voltage VSH of the signal line driving circuit itself is applied to the pixel. When video data (D0, D1)=(0, 1) is input and when video data (D0, D1)=(1, 0) is input, the average voltage of the signal line driving circuit is supplied to the pixel as long as the frequencies of the signals TM1 and TM2, respectively, are set at a value sufficiently higher than the cut-off frequency of the low-pass filter characteristics of the path from the output of the signal line driving circuit to the pixel. Thus, the average voltage of (m'VSH+n'VSL)/(m+n) is charged in the pixel.
In a conventional AD method, the linear region of the output stage analog buffers 230 is generally as narrow as about 70% of the supply voltage, so that it requires a high resistance-voltage process for fabricating the circuitry elements so as to be capable of withstanding a high supply voltage, which results in an increase in the cost. If a large and high-resolution display panel is to be driven, a large load is imposed on the output stage analog buffer 230 provided for each signal line, thereby deteriorating the display quality.
In the case of an AD type liquid crystal display device, it is required to process the analog video signal itself so that the display-luminance characteristics of the display device, i.e., the relationship between the signal level of the analog video signal and the display luminance of the pixel due to the liquid crystal, becomes linear. This results in an increase in the cost.
Moreover, an AD type liquid crystal display device is required to be driven by an alternating current (a.c. driving). This requires a high-speed polarity inversion signal generation circuit capable of processing the band of analog video signals, which results in an increase in the cost.
Moreover, in certain types of display panels, the application of a positive voltage and a negative voltage having the same absolute value to a pixel electrode can result in a difference between the absolute values of respective retained voltage levels. In other words, merely inverting the polarity of a video signal may create a difference between the positive and negative voltage levels retained in the pixel. This causes flickering of images, and may develop an after-image phenomenon.
On the other hand, although a conventional DD method requires only four kinds of external gray-scale voltages of V0 to V3 in the case where the video signal data D0 and D1 are 2-bit data, full-color display is generally considered to require 8-bit information for each color of red, blue, and green as video signal data. When conducting full-color display by a conventional DD method, 256 external gray-scale voltages (V0 to V255) are required; so that 256 analog switches (ASW0 to ASW255) are required, each being provided between the corresponding one of the external gray-scale voltages V0 to V255 and the signal line. Thus, according to a conventional DD method, as many external gray-scale voltages, and analog switches for each signal line, are required as the number of gray-scale levels. Accordingly, the number of gray-scale voltages and the number of analog switches for each signal line increases as the number of gray-scale levels increases. This results in an increase in the chip size when the circuitry is made into an LSI, thereby increasing the cost.
The above-mentioned binary multiple gray-scale signal line driving circuit eliminates the need of the external gray-scale voltages and analog switches as required by a conventional DD method, and therefore realizes a low-cost signal line driving circuit. However, when this method is applied to full-color display, it is required to input 8-bit information for each color of red, blue, and green as video signal data, and substantially as many digital gray-scale oscillation signals (corresponding to TM1 to TM2 described above), having different duty ratios, as the number of gray-scale levels. It is very difficult to input such a large number of control signals to the signal line driving circuit. If a television image or the like, which is originally an analog signal, is to be displayed, a high-speed and high-resolution analog/digital conversion circuit is required, thereby increasing the cost.
Also in the above-mentioned binary multiple gray-scale signal line driving circuit, it may be necessary to drive signal lines having load capacitance with a pulse waveform so as to repeat charging and discharging, depending on the frequencies of the digital gray-scale oscillation signals (corresponding to the signals TM1 and TM2 above). This results in an increase in the power consumption.
In certain types of display panels, the oscillation voltage of the output of the signal line driving circuit is not sufficiently averaged by the low-pass filter characteristics of the path from the output of the signal line driving circuit to the pixel. This deteriorates the display quality.